Branch-compression

For code without loops, the conditional branches and gotos need to be translated into if-then-else statements, from which the VHDL compiler will create combinational logic. The trouble is that constructs such as the one shown in figure 4 do not have equivalent if-constructs. These control-flow patterns can be generated by source-language goto statements or short-circuit logical operators. The algorithm devised in this work combines dominator tree and flow-graph information to define a ``merge node,'' where the two control flows of the conditional will merge (if ever). Statements must then be duplicated along each side of the conditional, until the merge node is reached, or all statements have been translated. Figure 5 shows the resultant VHDL for the quadruples in figure 4.

  

Figure 4: A flowgraph which can not be represented as an if-then-else statement without quadruple duplication.

  

Figure 5: Conversion of the program of figure 4 to VHDL.