A compiler, a general hardware design, and several benchmarks were created to evaluate programmable hardware's suitability for brute-force key search. The cryptographic algorithm was expressed in a high-level language and compiled to produce behavioral VHDL. The VHDL description was analyzed by Synopsys tools and targeted to the Xilinx XC4010 FPGA. Xilinx place-and-route tools were used on the final net-list.